The course will provide an overview of the typical issues designers face when they want to protect their circuits against Electrostatic Discharge. Through a set of basic and advanced case studies different on-chip ESD protection concepts are compared.
IC designers continue to combine ever more features in advanced digital Systems-on-Chips (SoCs) like analog to digital and digital to analog conversion, sensor interfaces, audio/video handling, high speed interfaces, optical links... The design of these circuits is complex and involves combining IP blocks from different sources.
On top of this functional design complexity, circuit designers face challenges related to ESD protection: on-chip ESD concepts used in general purpose I/O’s are not well suited for many specialty interfaces because they introduce high parasitic capacitance, series resistance and leakage current. Similar problems exist in BCD platforms for automotive applications and other high voltage applications. E.g. the amount of electronic circuits in cars has been steadily increasing to an average of more than 50 ASICs per car. Not only the number of circuits in cars has been expanding. Also the quality requirements have been continuously increasing. While on-chip ESD requirements are being lowered in consumer electronics the specifications for automotive parts have only been increased. LIN/CAN interfaces for instance must pass stringent system level ESD stress (IEC 61000-4-2) of more than 6kV. This increased requirement strongly limits the options for ESD protection. Furthermore there are many non-ESD requirements that affect the selection of the most appropriate ESD concept: Electrical OverStress (EOS), Electromagnetic compatibility (EMC) and of course (transient) latch-up. Drastic changes to the process platform (SOI, 3D-IC, FinFETS) can also cause new ESD challenges.